In high-speed input/output (I/O) links, an accurate measurement of the eye-width of the received signal is critically important. The output of a signal from a I/O Circuit transmitter is known commonly as an eye diagram. Eye diagrams helps to determine system level voltage and timing margin associated with a high speed I/O operation. The better the quality of the digital signal transmission, the wider the eye width and eye height will be.
In the current eye measurement technique, phase interpolator (PI) codes for eye center training are captured. After training, system margining is performed to push the clock edge to the right (or left) edge of the eye. A phase interpolator code for right (or left) edge of the eye is captured. The difference of phase interpolator codes between eye-center training and eye edge right (or left) is used to manually generate the right eye width (or left eye width) data in picoseconds. This process needs to refer to the phase interpolator differential non-linearity (DNL) characteristics collected through silicon validation processes.
The current eye measurement technique is a very tedious operation, involving a significant amount of manual labor. More importantly, to obtain highly accurate eye-width measurements, extensive silicon validation characterizations across multiple process/voltage/temperature variations would be required.
Other prior art eye measurement designs have flip-flop metastability issues, which affect the measurement precision.
Thus, there is a continuing need for an automated eye-width characterization method that overcomes the shortcomings of the prior art.